1. Field of the Invention
The present invention is related to semiconductor device manufacturing and more particularly to forming off chip connection pads for semiconductor integrated circuit (IC) chips.
2. Background Description
Typical semiconductor integrated circuit (IC) chips are multilayered units well known in the art with layers stacked such that layer features overlay one another to form individual devices and connect devices together. Individual layers normally are patterned lithographically using well known photolithographic techniques as applied to semiconductor manufacturing. State of the art chips have a surface layer populated by chip connection pads for input/output (I/O) and power connections, e.g., by wire bonding to the pads or with solder balls formed on the pads, e.g., for ball grid array (BGA) joining. Typically, the pads are of a self passivating material such as aluminum for wire bonding, which has an acceptable yield and, a relatively low fallout from pad failures and pad connection failures. Further, self passivating aluminum and connections to it can withstand the normal stresses encountered in chip use.
However, while aluminum may be self passivating and provide relatively reliable connections, aluminum is not amenable for plating and so, not an ideal choice for low cost IC wiring or for chip connections. Ideally, instead of aluminum, the I/O and power pads would be of a noble metal, e.g., gold or platinum, for high quality low resistance pads. Unfortunately, forming such noble metal pads has been difficult and has proven too costly to be implemented for widespread use. U.S. Pat. No. 6,368,484 B1 entitled “Selective Plating Process” to Volant et al. and U.S. Pat. No. 6,534,863 B2 entitled “Common Ball-Limiting Metallurgy for I/O Sites” to Walker et al., both assigned to the assignee of the present invention and incorporated herein by reference teach methods of forming electroplated pads on a semiconductor wafer. Both Volant et al. and Walker et al. teach forming a liner layer on the semiconductor wafer and selectively forming a seed layer at pad locations. Unfortunately, the seed layer may form in (undesired) locations other than at pad layers. Further, the liner and seed layers must be cleanly removed once the pads are formed without damaging underlying structures. So, while chip pads can be formed as taught by both Volant et al. and Walker et al., the result is a comparatively low chip yield, e.g., due to contamination introduced in pad formation, which further increases chip cost to a prohibitive level.
Thus, there is a need for low cost, low resistance, high yield and very reliable off-chip connections or pads and especially, for off-chip pads formed of a noble metal that can be electrolytically plated.